In wireless transmission, carrier frequency offset (CFO) estimation has long been a critical issue in orthogonal frequency-division multiplexing (OFDM) receivers, which have been selected as the basis for the high speed wireless local area network (WLAN) standards by the IEEE 802.11 standardization group. The packet preamble of OFDM specified by the IEEE standard consists of ten identical short OFDM symbols and two identical long symbols. These symbols can be used for the carrier frequency offset (CFO) estimation.
Please refer to FIG. 1, which is a block diagram of a signal processing circuit 10 of the prior art. The circuit 10 comprises a signal receiving circuit 120, an analog-to-digital convertor (ADC) 140, an auto-gain control circuit 160 and a baseband circuit 180. The auto gain control (AGC) circuit 160 comprises a signal detection circuit 164. The baseband circuit 180 comprises a carrier frequency offset (CFO) compensation circuit 184. Please also refer to FIG. 2, which is a flowchart of the corresponding signal processing method of the prior art.
In Step 210, the signal receiving circuit 120 receives a radio frequency (RF) signal and converts the RF signal into an analog signal, and the analog signal is then converted into a digital signal by the ADC 140. In Step 220, the AGC circuit 160 selects an initial gain, and for detecting signals of different strengths, the initial gain at the receiving end is set to the maximum. In Step 230, the AGC circuit 160 detects whether the signal is saturated. When the signal strength is small, since the default value of the gain is set to the maximum, the signal can be correctly received. When the signal strength is larger, since the default value of the gain is set to the maximum, the received signal is saturated. Once the signal is saturated, the receiving end becomes incapable of distinguishing the source of the signal, thus, the gain must be reduced gradually. The signal cannot be properly detected until the signal is no longer saturated.
If the signal is still in saturation, it proceeds to Step 240 and the AGC circuit 160 reduces the gain. The process then returns to Step 230 where the AGC circuit 160 detects again whether the signal is saturated or not. The above steps are repeated until the signal is not saturated, and the process proceeds to Step 260 where the signal detection circuit 164 detects whether the signal is the desired target signal. If the signal is not the desired target signal, the process returns to Step 210, waiting for the next receiving RF signal. If the signal is the desired target signal, the process proceeds to Step 270 to enter an RF steady state and close the AGC circuit 160 to save power. Subsequently, in Step 280, the carrier frequency offset (CFO) compensation circuit 184 detects the carrier frequency offset. In Step 290, the CFO compensation circuit 184 applies the CFO compensation. At that, the CFO compensation circuit 184 detects the CFO and performs the CFO compensation according to
            ∑              k        =        1            N        ⁢                  r        ⁡                  (                      t            +            k                    )                    ·                        r          *                ⁡                  (                      t            +            k            +            N                    )                      ,where r(t) is the receiving signal, and N is the period of the receiving signal.
FIG. 3 is a schematic diagram of the timing utilization for IEEE 802.11a/g/n wireless network specifications. For detecting signals of different strengths, the AGC circuit 160 sets the default value of the gain at the receiving end to the maximum. When the signal strength is small, since the AGC circuit 160 sets the default value of the gain to the maximum, the signal can be correctly received. However, when the energy of the signal is larger, since the AGC circuit 160 sets the default value of the gain to the maximum, the received signal is saturated. Once the signal is saturated, the receiving end becomes incapable of distinguishing the source of the signal, thus, the AGC circuit 160 must keep reducing the gain gradually. The signal cannot be properly detected until the signal is no longer saturated. The above step is time-consuming. If the energy of the signal is too large, the original time slots t1 to t7 for signal analysis are not enough for the auto-gain adjustment and the signal detection, so as to affect the CFO estimation by the CFO compensation circuit 184.
Therefore, there is an urgent need for a signal processing circuit and method thereof providing more time for processing the saturated signal, and demodulating the signal with the CFO correctly at the same time.